Physical Design Engineer (PnR / PPA / Timing Closure)

Role: Physical Design Engineer (PnR / PPA / Timing Closure)

Mountain View CA

Full Time

Job Description

We are looking for a Physical Design Engineer with strong expertise in Place & Route (PnR), Power Performance-Area (PPA) optimization, and timing convergence for advanced technology nodes.

Key Responsibilities

• Drive block-level physical design implementation from netlist to GDSII.

• Perform floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and physical verification.

• Optimize designs for Power, Performance, and Area (PPA) targets.

• Achieve timing closure across multiple corners and modes.

• Analyze and resolve setup, hold, transition, capacitance, and noise violations.

• Develop and maintain timing constraints (SDC) and STA signoff methodologies.

• Perform EMIR (Electromigration & IR Drop) analysis and closure.

• Collaborate with RTL, DFT, STA, and Signoff teams to ensure successful tapeout.

• Debug physical design issues and drive design convergence within project schedules.

Required Skills

• Strong experience in Physical Design and PnR flow.

• Hands-on expertise in:

o Floorplanning

o Placement & Optimization

o Clock Tree Synthesis (CTS)

o Routing

o Timing Closure

o Static Timing Analysis (STA)

o Timing Constraints (SDC)

o EMIR Analysis

o PPA Optimization

• Experience with industry-standard EDA tools such as:

o Synopsys Fusion Compiler / ICC2

o PrimeTime

o Cadence Innovus (optional)

o RedHawk / Voltus (EMIR)

• Good understanding of low-power design techniques and signoff methodologies.

Preferred Qualifications

• Bachelor's or Master's degree in Electrical/Electronics Engineering.

• Experience in advanced nodes (7nm/5nm/3nm preferred).

• Strong debugging and problem-solving skills.

• Experience working with cross-functional silicon teams.